The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various circuits and methods to implement voltage regulators for power management systems. One particular voltage regulator scheme often referred to as a low drop-out (LDO) voltage regulator typically was used for high efficiency power management systems such as for battery operated applications. LDO regulators can operate correctly even when the input voltage is less than one volt higher than the regulated output voltage. FIG. 1 schematically illustrates some elements of such a typical prior art low drop-out (LDO) voltage regulator. Typically, a battery was connected between power input and common terminals of the LDO regulator. A transistor 102 received power from the battery and supplied current to an output capacitor 105 and to a load 108. Output capacitor 105, generally illustrated by a dashed box, typically had two components, a pure capacitive element 107 as well as a resistive element 106, generally referred to as an equivalent series resistance or ESR. A single stage differential amplifier was utilized as an error amplifier 101 in order to control the voltage on capacitor 105. A voltage divider 104 formed a feedback voltage that was indicative of the output voltage on output 110. Amplifier 101 compared the feedback voltage to a reference voltage 103 and drove the gate of transistor 102 to provide the desired output voltage on capacitor 105.
This circuit structure produced a dominant pole that was controlled by the input impedance of load 108 and by the output impedance of transistor 102. Since the transistor 102 output impedance varied with the current through transistor 102, the dominant pole moved in frequency as the output current varied. Further, the ESR and the capacitance of capacitor 105 formed a zero at a frequency determined by the product of resistance 106 and capacitance 107. Capacitor 105 had a large ESR, thus the resulting high frequency zero contributed to the stability at high frequencies and provided sufficient phase margin to provide a stable output voltage for the output current value supplied by regulator 100. However, if the ESR value decreased, the zero moved to a much higher frequency and could no longer contribute to the stability of the LDO. This resulted in an unstable output voltage at some if not all of the output currents provided by the LDO. Such low ESR values are typical of ceramic capacitors that are often utilized for output capacitors.
Accordingly, it is desirable to have a method of forming a power management unit that has a stable output for small ESR values.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor.